Without limiting the scope of the invention, its background is described in connection with a dynamic random access memory (DRAM), as an example.
Heretofore, in this field, DRAM memory cells have used planar capacitors for simplicity of manufacturing. As the capacity of devices using these cells has increased, the geometry of these memory cells has steadily decreased until planar structures have become difficult to use reliably. As the memory cell geometry has decreased, so has the capacitor size and storage capacitance. However, a decrease in storage capacitance leads to lowered signal-to-noise ratios and errors due to alpha particle hits.
Prior art attempts to overcome these problems have included trench capacitor cells in which a capacitor is formed in the sidewall of a trench formed in a semiconductor substrate. This structure also has associated difficulties in the process of forming deep, small feature trenches.
Another prior art capacitor cell is disclosed in a U.S. Pat. No. 4,742,018 by Kimura, et al. In accordance with the claims of this invention, a process for producing a DRAM cell having a stacked capacitor is disclosed. In the process disclosed therein, a MOSFET is formed having a gate electrode, a drain region, and a source region in a semiconductor substrate. The process further comprises the steps of forming a first conductor layer on the substrate electrically connected to the drain region and depositing a first insulator film on the first conductor layer except for a necessary portion. Further disclosed therein is the step of depositing a second conductor on the first insulator so that the second conductor layer is electrically connected to the first conductor layer. Subsequently, a portion of the second conductor is removed, except for a necessary portion. The first insulator is then removed and a second insulator film is formed on the first and second conductor layers. Finally, a third conductor layer is formed on said second insulator film. Difficulties with this method include having a separate mask for first and second conductor layers which can introduce alignment problems and adds process steps.
Yet another prior art capacitor cell is disclosed in an article in International Electronic Devices Meeting, 1988, pp. 592-595 by Ema, et al. In this article, Ema, et al., disclose a stacked memory cell in which the capacitor cell is three-dimension. This prior art stacked capacitor is composed of a poly-Si--Si.sub.3 N.sub.4 --poly-Si structure. A difficulty with this prior art capacitor cell, as well as in others including the Kimura embodiment relates to the minimum spacing between capacitor cells. In these known prior art embodiments the minimum spacing between capacitor cells can be no less than the minimum feature size of the lithographic process used.